When looking at future embedded systems and their design, especially (but not exclusively) in the multi‐ media domain, we observe several problems: 

  • high performance (10 GOPS and far beyond) has to be combined with low power (many systems are mobile); 
  • time‐to‐market (to get your design done) constantly reduces; 
  • most embedded processing systems have to be extremely low cost; 
  • the applications show more dynamic behavior (resulting in greatly varying quality and performance requirements);
  • more and more the designer requires flexible and programmable solutions;
  • huge latency gap between processors and memories;

and

  • design productivity does not cope with the increasing design complexity.
 In order to solve these problems we foresee the use of programmable multi‐ processor platforms, having an advanced memory hierarchy, this together with an advanced design trajectory. These platforms may contain different processors, ranging from general purpose processors, to processors which are highly tuned for a specific application or application domain. This course treats several processor architectures, shows how to program and generate (compile) code for them, and compares their efficiency in terms of cost, power and performance. Furthermore the tuning of processor architectures is treated Several advanced Multi‐Processor Platforms, combining discussed processors, are treated. A set of lab exercises complements the course.